Semiconductor devices such as logic and memory devices are typically fabricated by a sequence of processing steps applied to a specimen. The various features and multiple structural levels of the semiconductor devices are formed by these processing steps. For example, lithography among others is one semiconductor fabrication process that involves generating a pattern on a semiconductor wafer. Additional examples of semiconductor fabrication processes include, but are not limited to, chemical-mechanical polishing, etch, deposition, and ion implantation. Multiple semiconductor devices may be fabricated on a single semiconductor wafer and then separated into individual semiconductor devices.
Metrology processes are used at various steps during a semiconductor manufacturing process to detect defects on wafers to promote higher yield. Optical metrology techniques offer the potential for high throughput without the risk of sample destruction. A number of optical metrology based techniques including scatterometry and reflectometry implementations and associated analysis algorithms are commonly used to characterize critical dimensions, film thicknesses, composition, overlay and other parameters of nanoscale structures.
Semiconductor devices are often fabricated by depositing a series of layers on a substrate. Some or all of the layers include various patterned structures. The relative position of structures both within particular layers and between layers is critical to the performance of completed electronic devices. Overlay refers to the relative position of overlying or interlaced structures on the same or different layers of a wafer. Overlay error refers to deviations from the nominal (i.e., desired) relative position of overlying or interlaced structures. The greater the overlay error, the more the structures are misaligned. If the overlay error is too great, the performance of the manufactured electronic device may be compromised.
Scatterometry overlay (SCOL) metrology techniques have been applied to the characterization of overlay errors. These methods are based primarily on differential measurements of optical signals corresponding to diffraction from pairs of targets each with programmed overlay offsets. The unknown overlay error is extracted based on these differential measurements.
In most existing methods, overlay error is characterized based on a metric sensitive to asymmetry of the structure. In one example, existing angle-resolved scatterometry overlay (SCOL) involves a characterization of the asymmetry between the +1 and −1 diffracted orders that is indicative of overlay error. However, relying on asymmetry as the indicator of overlay error is problematic because other asymmetries such as line profile asymmetry or beam illumination asymmetry couple into the overlay-generated asymmetry in the measurement signal. This results in an inaccurate measurement of overlay error.
In existing methods, overlay error is typically evaluated based on measurements of specialized target structures formed at various locations on the wafer by a lithography tool. The target structures may take many forms, such as a box in box structure. In this form, a box is created on one layer of the wafer and a second, smaller box is created on another layer. The localized overlay error is measured by comparing the alignment between the centers of the two boxes. Such measurements are taken at locations on the wafer where target structures are available.
Unfortunately, these specialized target structures often do not conform to the design rules of the particular semiconductor manufacturing process being employed to generate the electronic device. This leads to errors in estimation of overlay errors associated with actual device structures that are manufactured in accordance with the applicable design rules. For example, image-based overlay metrology often requires the pattern to be resolved with an optical microscope that requires thick lines with critical dimensions far exceeding design rule critical dimensions. In another example, angle-resolved SCOL often requires large pitch targets to generate sufficient signal at the +1 and −1 propagating diffraction orders from the overlay targets. In some examples, pitch values in the range 500-800 nm may be used. Meanwhile, actual device pitches for logic or memory applications (design rule dimensions) may be much smaller, e.g., in the range 100-400 nm, or even below 100 nm.
In one existing method, two double grating targets with programmed overlay shift of +d and −d are used to measure +1 and −1 diffraction order intensity of both targets. Asymmetry in the +1 and −1 diffraction order signals is a measure of overlay shift between layers in the stack. Measured asymmetry is linearly proportional to overlay error and the pair of targets is used to calculate the proportion. Further details are described in “Performance of ASML YieldStar pDBO overlay targets for advanced lithography nodes C028 and C014 overlay process control,” Proc. SPIE 8681, Metrology, Inspection, and Process Control for Microlithography XXVII, 86811F (Apr. 18, 2013) and “Optical Scatterometry For In-Die Sub-Nanometer Overlay Metrology,” 2013 International Conference on Frontiers of Characterization and Metrology for Nanoelectronics (FCMN2013), Mar. 25-28, 2013, NIST, Gaithersburg, Md., USA.
A disadvantage of this approach is that measurements of +1 and −1 diffraction order signals require large pitch, non-design rule targets. Another disadvantage is that the measurement sensitivity depends on properly matching the illumination wavelength to the grating pitch of the metrology targets. Since the available illumination wavelengths are typically limited, this limits overlay sensitivity especially when the layers between the gratings are opaque for the available wavelengths.
In another existing method, at least three double grating targets each with different, programmed overlay shifts are illuminated and zero order diffraction light is collected over a large band of incidence space. Signal differences between every pair of targets are calculated. The resulting combination of differential signals is proportional to overlay. Measured overlay and the known, programmed overlay of the targets are used to calculate overlay error. Further details are described in “Overlay control using scatterometry based metrology (SCOL™) in production environment,” Metrology, Inspection, and Process Control for Microlithography XXII, Proc. of SPIE Vol. 6922, 69222S, (2008). A disadvantage of this approach is that six or eight cell targets are typically required to measure both X and Y overlay.
In some other examples, a model based approach to overlay measurement is employed. In one example, a model of a double-grating target is parameterized including an overlay parameter. Electromagnetic modeling of light scattering is used to simulate signals collected from the double-grating target. Nonlinear regression of the simulated signals is performed against measured signals to estimate overlay error. This approach requires accurate modeling of the structure and the material properties. The modeling effort is complex and time consuming, and the resulting regression routines require a large amount of computing effort and time to reach a result.
Future overlay metrology applications present challenges for metrology due to increasingly small resolution requirements and the increasingly high value of wafer area. Thus, methods and systems for improved overlay measurements are desired.
Image based measurements typically involve the recognition of specific target features (e.g., line segments, boxes, etc.) in an image and parameters of interest are calculated based on these features. Typically, the specialized target structures are specific to the image processing algorithm. For example, the line segments associated with an overlay target (e.g., box-in-box target, frame-in-frame target, advanced imaging metrology (AIM) target) are specifically designed to comply with the specifics of the algorithm. For this reason, traditional image based metrology algorithms cannot perform reliably with arbitrary targets or device structures.
In addition, information is lost because the algorithms are applied to limited areas of the image. By selecting particular line edges, etc. as the focal point for analysis, contributions that might be made by other pixels in the image are ignored.
Moreover, traditional image based algorithms are sensitive to process variations, asymmetry, and optical system errors as these algorithms lack a systematic way to capture the impact of these error sources on the captured images.
In semiconductor manufacture, and patterning processes in particular, process control is enabled by performing metrology on specific dedicated structures. These dedicated structures may be located in the scribe lines between dies, or within the die itself. The use of dedicated metrology structures may introduce significant measurement errors. Discrepancies between actual device structures and dedicated metrology targets limit the ability of metrology data to accurately reflect the status of the actual device features in the die. In one example, discrepancies arise due to location dependent differences in process loading, pattern density, or aberration fields because the dedicated metrology targets and actual device structures are not collocated. In another example, the characteristic feature sizes of the dedicated metrology structures and the actual device structure are often quite different. Hence, even if the dedicated metrology target and the actual device structure are in close proximity, discrepancies result from differences in size. Furthermore, dedicated metrology structures require space in the device layout. When sampling density requirements are high, dedicated metrology structures crowd out actual device structures.
Future metrology applications present challenges for image based metrology due to increasingly small resolution requirements and the increasingly high value of wafer area. Thus, methods and systems for improved image based measurements are desired.